The storage of fixed programs in digital computing systems is usually accomplished in fixed memories known as read only memories (ROM) or as they are sometimes calld read only stores (ROS). These memories are built in matrix form with multiple rows and columns, the memory devices or, as they are sometimes called, memory cells being located at the intersections of row and column lines. It is known that any of a number of electrical components may be used as the memory cell. For example, one of the earliest memory cells for ROMs was a resistor selectively connected to the intersections of the row and column lines. The bit status at each bit location was determined by the presence or absence of a resistance at the location. In initial stages of manufacture, resistors were located at each bit position to produce a conductive path between the row line and the intersecting column line. To program bit positions, the resistors at certain bit positions, selected by the fixed program, are removed, usually by a simple burnout process. This eliminates the row to column conductive path at the bit positions with burnt out resistors. The presence or absence of a conductive path at the bit position determines the bit status, that is, the logic level of the bit. This method of memory personalization is often called electrical personalization, for the personalization is accomplished with the application of electric energy to the memory matrix at the end of the manufacturing process. An example of a ROM with resistor elements as the memory cells is shown in U.S. Pat. No. 3,246,315 which issued Apr. 12, 1966 to C. W. Gear and is assigned to the assignee of the invention disclosed herein.
Diodes, PN junction trasistors and field effect transistors are also commonly used as memory cells in read only memories. While electrical personalization is available for memory cells comprised of diodes, PN junction transistors and field effect transistors, another form of personalization, is sometimes used. This personalization technique which involves altering device characteristics during the manufacturing process according to the data state desired has been successfully and advantageously used. Depending on the process involved, personalization may occur during the early stages of the manufacturing process, often called Front End Of the Line (FEOL) personalization or during late stages of the manufacturing process, called Back End Of the Line (BEOL) personalization. A ROM with field effect transistor memory cells personalized by device modification during manufacture is disclosed in U.S. Pat. No. 4,208,727 which issued to Redwine et al on June 17, 1980.
It is a continuing goal of those who manufacture read only stores to maximize the number of bits per memory chip while maintaining small chip size. It is also often desirable to hold off memory personalization until the latter stages of the manufacturing process to allow late changes in the fixed program to be incorporated into the memory.